Memory systems are used for storage of data, program code, and/or other information in many electronic products, such as personal computer systems, embedded processor-based systems, video image processing circuits, portable phones, and the like. Ferroelectric memory, sometimes referred to as “FRAM” or “FERAM”, is a non-volatile form of memory commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) cell configurations, in which each memory cell includes one or more access transistors and one or more cell capacitors formed using ferroelectric dielectric material. The non-volatility of an FERAM memory cell results from a bi-stable or multi-stable characteristic of the ferroelectric dielectric material in the cell capacitor(s), wherein the ferroelectric material has multiple electrically distinguishable stable states. Ferroelectric memory is often fabricated in stand-alone memory integrated circuits (ICs) and/or in other semiconductor products such as logic circuits having on-board non-volatile memory, microprocessors, DSPs, communications chips, etc. The ferroelectric memory cells are typically organized in an array architecture, such as folded-bitline, open-bitline, etc., wherein the individual cells are selected by plateline and wordline signals from address decoder circuitry, with the data being read from or written to the cells along bitlines using latch or sense amp circuits. In a typical 1T1C memory cell, a ferroelectric capacitor is coupled between a plateline signal and a cell storage node at a source/drain of a MOS cell transistor. The other source/drain of the cell transistor is connected to a bitline, and the transistor gate is connected to a wordline control signal to selectively couple the capacitor with the bitline during read and write operations.
The ferroelectric memory arrays are typically constructed in a device wafer along with CMOS logic circuits, wherein the cell transistors are formed concurrently with logic transistors in the device, and the ferroelectric capacitors are constructed in a capacitor layer above the wafer substrate. For example, the construction of the ferroelectric cell capacitors may be integrated into a CMOS fabrication process flow after transistor formation (e.g., after standard ‘front-end’ processing), and prior to the metalization or interconnection processing (e.g., before ‘back-end’ processing). In a typical integration of ferroelectric capacitors in a CMOS process flow, transistors are formed on/in a semiconductor body, and a pre-metal dielectric (PMD) layer is constructed over the transistors, including tungsten contacts extending through the PMD level dielectric to the gate and source/drain terminals of the transistors. Ferroelectric cell capacitors are then constructed in a first inter-level or inter-layer dielectric layer (e.g., ILD0) above the PMD level, where one of the cell capacitor electrodes (e.g., a lower or bottom electrode) is connected to a cell transistor terminal (e.g., typically a source/drain) through one of the tungsten PMD contacts, wherein interconnection of the other capacitor electrode (the top or upper electrode) and the remaining transistor terminals with other components (e.g., signal routing) is provided in one or more metalization layers or levels above the ILD0 level.
When a selected cell is read (e.g., along with other cells along a target array row), pulsing the capacitor plateline terminal causes a voltage to develop on the bitline because the cell capacitor discharges through the pass gate transistor to the bitline. Once the bitline signal is amplified by the sense amp, the bitline goes high or low, depending on whether the data is a binary “1” or a “0”, respectively. Any excess charge at the storage node of the cell, however, may disrupt or disturb the sensing of the stored data, and in some cases may cause incorrect data to be read out of the cell. In particular, leaky cell transistors may cause unwanted charging or discharging of the cell storage node, sometimes referred to as storage node disturbance.
One possible cause of storage node disturbances occurs where the cell is not selected for a read or write access (e.g., the associated wordline is low and the transistor is theoretically off), and the cell does not receive a plateline pulse. In this situation, accesses to other rows in the memory array along the bitline will cause the bitline voltage to rise. If the non-selected cell transistor leaks, the storage node of the non-accessed cell can acquire or lose charge (the storage node voltage changes) while the associated plateline is low. For example, where the data on the bitline is a “1” (e.g., the bitline is at a high voltage), leakage through the cell transistor may cause charge buildup at the storage node, thereby increasing the voltage across the cell capacitor. Even while reading a “0” data, the voltage on the bitline can rise above 0 V, resulting in a rise or gain in storage node voltage for the cell. This form of storage node disturbance is possible whether the non-accessed cells receive a plateline pulse or not. Another cause may occur where plateline drivers are shared among selected and non-selected rows, wherein leakage through the non-selected cell transistors can result in storage node voltage changes when a plateline pulse is applied to the non-selected cell capacitors.
Such acquired storage node charge may not be dissipated prior to reading the affected cell. Moreover, repeated accesses to other cells may cause this acquired charge to increase over time, wherein the storage node voltage rises. As a result, the signal margin of the system is decreased, and the cell capacitor may even be depolarized from its intended (e.g., programmed) state. Furthermore, such storage node disturbances may be worsened through wordline coupling that temporarily raises the wordline voltage while a different (adjacent) row is being accessed.
Circuit designs can be modified to address these storage node voltages. However, these approaches require extra circuitry thus increasing the chip area occupied by the memory cells and associated circuitry, and may increase the device power consumption and the time required for a memory access operation. Consequently, there is a need for improved ferroelectric memory devices and techniques by which cell storage node disturbances can be mitigated or avoided without increasing the memory cell area and without increasing the memory access time.